In a semiconductor fabrication process, it needs to dice a wafer having semiconductor devices formed on its surface into a plurality of chips, then each of the chips is packaged to form integrated circuits or chip devices. For the wafer level chip size packaging (WLCSP) technology, the wafer is tested after being packaged; and then the packaged wafer is diced in individual ready-to-use chips. The size of the packaged chip is identical to the size of the bare chip. The size of the chips after the WLCSP is able to reach the high level miniaturization; and the cost of the chips is significantly reduced by decreasing the chip size and increasing the wafer size.
With the continuous development of the semiconductor manufacturing technology, the fabrication methods of semiconductor devices and the device structures of the semiconductor devices have become more and more complex, thus the semiconductor fabrication processes performed on only one side of a wafer are unable to match the continuous development of the semiconductor manufacturing technology. Some fabrication processes have been developed to fabricate devices and chips on both sides of the wafer, such as the fabrication process of MEMS pressure sensors, the fabrication process of the backside illuminated (BSI) image sensors, the fabrication process of the through silicon via (TSV) structures, or wafer packaging processes, etc. Such fabrication processes all need to perform back-end-of-line (BEOL) processes on the other side of the wafer after forming semiconductor device structures on one side of the wafer. Then, the wafer is diced into chips after the BEOL processes.
In order to prevent the semiconductor device structures formed on the one side of the wafer from being damaged when the BEOL processes are performed on the other side of the wafer, a supporting wafer is usually bonded with the one side of the wafer having the semiconductor device structures. The supporting wafer may be used to protect the semiconductor device structures on the one side of the wafer during the BEOL processes; and the subsequent edge trimming process, grinding process and the dicing process, etc.
Because the wafer bonding process for bonding the supporting wafer with the wafer having the devices structures includes a pressing process (pre-bonding) and a thermal annealing process, the wafer bonding process may affect the properties of the device structures formed on the wafer. Therefore, the existing methods usually test the electrical properties of the device structures after etching the supporting wafer to expose the testing structures. The testing results may be used to determine the effect to device structures formed on the surface of the wafer caused by the wafer bonding process.
However, because the testing procedure is performed after the wafer bonding process, the testing results may not be precise because of the wafer bonding process and other processes; and it may affect the further improvements of the fabrication process. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.